1. Field of the Invention
The present invention relates to computer processing systems having dual execution units. More specifically, logic is provided that allows a second execution unit to operate even when interruptable instructions are executing on the first execution unit.
1. Description of Related Art
Conventionally, in a dual execution unit processing system, when an interruptable instruction is encountered on a first execution unit, the second unit is held off until that instruction executes. Since, many common instructions can potentially cause interrupts, the performance of the processing system is degraded if instructions executing on the second execution unit are held depending on whether the instructions executing on the first unit causes an interrupt.
In a dual execution unit processor design, it is often necessary to cancel the second instruction that has just executed. Reasons for cancelling this instruction may be the occurrence of an interrupt which is caused by the execution of the first instruction. Interrupts may occur due to a "page fault" occurrence, (i.e. a page is not in memory), or because of a trap type interrupt. Since both instructions execute in the same machine cycle, the second instruction may have altered an architected register, i.e. one that is capable of being altered by the software, which must now be restored to its previous state. For example if a load instruction is executing in the first execution unit and an add instruction with overflow enable is executing in the second unit, and the load causes an interrupt, the bits set by the add instruction in the fixed point exception register (XER) must be restored to their previous values, because the add instruction must be cancelled due to the interrupt.
Thus, the problem is restoring the modified contents of architected registers in a multi-execution unit design when the instruction executing in the second execution unit is cancelled, due to a side effect caused by the execution of the first instruction executing in the first execution unit. It can be seen that this problem does not exist with architected registers that are modified during the write back cycle (not the execution cycle) because the interrupt is known during write back. Therefore, if an actual interrupt is generated during the execute cycle, the contents of these registers will contain the machine state as it was prior to the interrupt. This is because the actual interrupt is not identified until the write back cycle, such that update of the registers which are normally updated during the write back cycle is prevented. Thus, the contents of these registers will not be modified during the write back cycle. While those registers that are updated during the execute cycle will have to be restored.
IBM Technical Disclosure Bulletin, volume 35, no. 1B, June 1992, Page 398-399 discusses a multiple execution unit processor including a counter that tracks how many floating point unit (FPU) instructions have moved beyond the final stage of the fixed point unit (FXU) pipeline. The counter is incremented when an instruction that was also sent to the FPU moves beyond the final stage of the FXU and is decremented when the FPU completes an instruction. The system only allows the FPU to complete an instruction when the counter has a value greater than zero such that instructions are prevented from finishing.
IBM Technical Disclosure Bulletin, volume 32, no. 4A, September 1989, page 474, describes a system for fast interrupt response in pipelined processors. An interrupt state register (ISR) is used in the data flow that makes all instructions transparent to interruption. The ISR is an additional register which, in addition to status registers saves pipeline state parameters which are restored at the end of interrupt service by inclusion of a RESTORE instruction.
U.S. Pat. Nos. 5,148,530 and 4,901,222 describe a method of executing instructions by altering an address in a system with a virtual memory addressing scheme. The virtual address is incremented or decremented during the read out cycle of the previous operand. If the operand is not in physical memory, then the content of a base register is restored to its original value. This system backs out a software instruction after execution has begun.
U.S. Pat. No. 4,766,566 generally describes a processing system with dual special purpose execution units. U.S. Pat. No. 4,912,628 is a virtual machine system that includes a special program which provides suspend and resume control functions. This program seizes control of the machines external interrupt controls and directs all incoming interrupts to the program itself, rather than allowing the virtual machine to handle the interrupts. The machine is later restored to operation and the user's task is resumed from its interrupted point by restoring all register content. U.S. Pat. No. 4,589,065 performs a storage address validity check in a single cycle, in the event that trap exception does not cause an interrupt. If an interrupt does occur, more cycles will be needed.
It can be seen that none of these conventional systems include a general purpose dual execution unit processing system that determines if an instruction in the second execution unit modifies architected registers in the execute cycle and provides backup logic for restoring these registers should an interrupt be caused by instruction on first unit.